The present invention relates in general to the fabrication of semiconductor wafers, and, more particularly, to a method of reducing static electric charges on the surface of wafers resulting from plasma deposition.
Semiconductor processing requires the deposition of conductive materials on semiconductor wafers. Typically, plasma deposition, in the form of physical vapor deposition (PVD) or plasma enhanced chemical vapor deposition (PECVD), is used to deposit the conductive material on the semiconductor wafer as processing temperatures are significantly lower than non-plasma deposition methods. Plasma deposition is carried out in a plasma chamber with the wafer being secured on top of a wafer platform. Typically, the wafer is physically secured to the wafer platform by a clamping ring which engages an outer portion of the top surface of the wafer. The wafer platform is typically conductive so that the bottom surface of the wafer is electrically coupled to the wafer platform. The clamping ring is electrically coupled to the wafer platform such that the top surface of the wafer is also electrically coupled to the wafer platform.
An electrical bias is then applied to the wafer platform in order to control the plasma deposition process. The electrical bias sets up a negative potential on the wafer to attract the positive ions from the plasma. The topology of the formed layer is controlled by adjusting the applied electrical bias. Typically, the conductive material is applied over a layer of insulating material in order to form desired contacts, interconnects, or the like. While the clamping ring is electrically coupled to the wafer platform, the top surface of the wafer is not shorted to the wafer platform as the top surface of the wafer is insulated by the layer of insulating material. Once the plasma is generated, the top surface of the wafer is continually charged as the conductive material is deposited thereby forming a potential difference between the bottom surface of the wafer and the top surface of the wafer. This potential difference may lead to arcing through the wafer causing damage to one or more dies on the wafer.
Accordingly, there is a need for a process of depositing conductive materials over an insulating layer in which the risk of arcing through the wafer is reduced. Preferably, such a process would be inexpensive, easy to implement, would not entail excess processing steps, and would not adversely affect the quality of the deposited conductive layer.